Generally, class-D amplifiers can be classified into a pulse-width modulation (PWM) type and a sigma-delta (Σ-Δ) type, and the Σ-Δ class-D amplifiers can be further classified into 1-bit Σ-Δ class-D amplifiers and 1.5-bit Σ-Δ class-D amplifiers. The terms “1-bit” and “1.5-bit” refer to the number of voltage levels outputted from a quantizer, also known as “resolution”. More specifically, “1-bit” means that an input signal is quantized into two voltage levels, for example with the logic “0” and logic “1”, as disclosed in U.S. Pat. No. 5,777,512 to Tripathi et al. Due to high switching loss, 1-bit Σ-Δ class-D amplifiers have low conversion efficiency under small or no input signal conditions. To reduce the switching loss and thereby improve the conversion efficiency, 1.5-bit Σ-Δ class-D amplifiers have been proposed, for example by U.S. Pat. Nos. 5,077,539 and 7,170,340, which quantize an input signal into three voltage levels.
FIG. 1 is a block diagram of a 1.5-bit Σ-Δ class-D amplifier 10 which includes a control circuit having three integrators 12, 14 and 16, each may be of a continuous-time type or a discrete-time type, to convert differential input signals VINP and VINN that are in opposite phases to each other into signals SOP and SON, and a 1.5-bit quantizer 18 to quantize the signals SOP and SON into a digital signal having three voltage levels for a switching logic 20 to operate a power stage 22.
FIG. 2 shows a typical circuit of the power stage 22. By using the switching logic 20 to determine control signals UGA, LGA, UGB and LGB, the quantized digital signals +1, 0 and −1 may switch the MOSes 26, 28, 30 and 32 in an H-bridge to provide different voltages for a load 40. For example, Table 1 lists the switching logics, i.e., the output of the 1.5-bit quantizer 20 and the status of the H-bridge. When the quantized output is +1, the MOSes 26 and 32 are turned on and the MOSes 28 and 30 are turned off, in which case current will flow from the voltage supply Vdd to the ground terminal GND through the MOS 26, the load 40 and the MOS 32, and the voltage across the load 40 is a first voltage. When the quantized output is −1, the MOSes 26 and 32 are turned off and the MOSes 28 and 30 are turned on, in which case current will flow from the voltage supply Vdd to the ground terminal GND through the MOS 30, the load 40 and the MOS 28, and the voltage across the load 40 is a second voltage. When the quantized output is 0, the MOSes 28 and 32 are turned on and the MOSes 26 and 30 are turned off, in which case the differential output terminals 34 and 36 are both grounded, and the voltage across the load 40 is zero.
TABLE 1Quantized OutputStatus of H-bridge+1UGA, LGB off; UGB, LGA on−1UGB, LGA off; UGA, LGB on0LGA, LGB off; UGA, UGB on
1.5-bit Σ-Δ class-D amplifiers have higher resolution and better efficiency than 1-bit Σ-Δ class-D amplifiers, but suffer from nonlinear variation of the voltage across the load 40.
Ideally, the MOSes 26 and 30, the voltage divider resistors R1-R4 in the H-bridge are matched with each other such that the voltage across the load 40 will vary in a linear way. For example, as shown by the dashed straight line 104 in FIG. 3, if the first voltage is 1V, then the second voltage will be −1V, and the voltage across the load 40 varies linearly. In real circuits, however, the MOSes 26 and 30, the resistors R1-R4 are generally mismatched with each other. For example, as shown by the curve 102 in FIG. 3, the first voltage will be 1.1V when the quantized output is +1, the second voltage will be −0.9 V when the quantized output is −1, and the voltage across the load 40 is still zero when the quantized output is 0. Thus, the curve 102 is not a straight line, and the voltage across the load 40 varies nonlinearly. This nonlinear output is divided by the resistors R1, R2 and R3, R4 to generate feedback signals LX_P and LX_N for the integrator 12, and causes the large harmonic distortions (THD+N) in the output spectrum, leading to degradation in THD+N of the class-D amplifier.
U.S. Pat. No. 6,472,933 to Hsu teaches a quaternary switching method for the H-bridge, which switches the H-bridge between four states, i.e. +1, 0H, 0L and −1, to improve the linearity in the voltage variation across the load to improve the THD+N.